The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to an interconnect structure containing conductive features having dimensions that are less than 50 nm and a method of forming the same.
Generally, semiconductor devices include a plurality of circuits that form an integrated circuit (IC) fabricated on a semiconductor substrate. A complex network of signal paths will normally be routed to connect the circuit elements distributed on the surface of the substrate. Efficient routing of these signals across the device requires formation of multilevel or multilayered schemes, such as, for example, single or dual damascene wiring structures. The wiring structure, which may also be referred to as an interconnect structure, typically includes copper, Cu, since Cu based interconnects provide higher speed signal transmission between large numbers of transistors on a complex semiconductor chip as compared with aluminum, Al, based interconnects.
Within a typical interconnect structure, metal vias run perpendicular to the semiconductor substrate and metal lines run parallel to the semiconductor substrate. Further enhancement of the signal speed and reduction of signals in adjacent metal lines (known as “crosstalk”) are achieved in today's IC product chips by embedding the metal lines and metal vias (e.g., conductive features) in a dielectric material having a dielectric constant of less than 4.0.
There are two common methods of forming interconnect structures. The first known method of forming interconnect structures is referred to in the art as a subtractive process. In the subtractive process, a layer of metal is provided on a substrate and then the layer of metal is subjected to a patterning process which provides at least one metal portion from the layer of metal. A dielectric material is then provided and thereafter a planarization process may be performed to provide a completed interconnect structure to complete an interconnect structure.
The second known method of forming interconnect structures is referred to in the art as a damascene process. In a damascene process, a dielectric material is first provided on a substrate. At least one opening is then formed into the dielectric material by lithography and etching. Next, a conductive metal is deposited within the at least one opening and atop the dielectric material. A planarization process can follow the deposition of the conductive metal to complete an interconnect structure.
The aforementioned methods of forming interconnect structures are reaching their limits and there is thus a need for providing an alternative method of forming interconnect structures which is capable of providing conductive features that have a dimension that is less than 50 nm.